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X28HC256
256k, 32k x 8-Bit
Data Sheet May 7, 2007 FN8108.2
5V, Byte Alterable EEPROM
The X28HC256 is a second generation high performance CMOS 32k x 8 EEPROM. It is fabricated with Intersil's proprietary, textured poly floating gate technology, providing a highly reliable 5V only nonvolatile memory. The X28HC256 supports a 128-byte page write operation, effectively providing a 24s/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down. Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years.
Features
* Access time: 70ns * Simple byte and page write - Single 5V supply - No external high voltages or VP-P control circuits - Self-timed - No erase before write - No complex programming algorithms - No overerase problem * Low power CMOS - Active: 60mA - Standby: 500A * Software data protection - Protects data against system level inadvertent writes * High speed page write capability * Highly reliable Direct WriteTM cell - Endurance: 1,000,000 cycles - Data retention: 100 years * Early end of write detection - DATA polling - Toggle bit polling * Pb-free plus anneal available (RoHS compliant)
Block Diagram
X BUFFERS LATCHES AND DECODER A0 TO A14 ADDRESS INPUTS Y BUFFERS LATCHES AND DECODER I/O BUFFERS AND LATCHES 256kBIT EEPROM ARRAY
I/O0 TO I/O7 CE OE WE DATA INPUTS/OUTPUTS CONTROL LOGIC AND TIMING
VCC VSS
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X28HC256 Ordering Information
PART NUMBER X28HC256DI-15 X28HC256DM-15 X28HC256DMB-15 X28HC256EMB-15 X28HC256FMB-15 X28HC256J-15*, ** X28HC256JZ-15* (Note) X28HC256JI-15*, ** X28HC256JIZ-15* (Note) X28HC256JM-15* X28HC256KI-15 X28HC256KM-15 X28HC256KMB-15 X28HC256P-15 X28HC256PZ-15 (Note) X28HC256PI-15 X28HC256PIZ-15 (Note) X28HC256PM-15 X28HC256SI-15* X28HC256SIZ-15* (Note) X28HC256SM-15 X28HC256D-12 X28HC256DI-12 X28HC256DM-12 X28HC256DMB-12 X28HC256EI-12 X28HC256EM-12 X28HC256EMB-12 X28HC256FMB-12 X28HC256J-12* X28HC256JZ-12* (Note) X28HC256JI-12* X28HC256JIZ-12* (Note) X28HC256KI-12 X28HC256KM-12 X28HC256KMB-12 X28HC256P-12 X28HC256PZ-12 (Note) X28HC256PI-12 PART MARKING X28HC256DI-15 RR X28HC256DM-15 RR C X28HC256DMB-15 C X28HC256EMB-15 C X28HC256FMB-15 X28HC256J-15 RR X28HC256J-15 ZRR X28HC256JI-15 RR X28HC256JI-15 ZRR X28HC256JM-15 RR X28HC256KI-15 RR X28HC256KM-15 RR C X28HC256KMB-15 X28HC256P-15 RR X28HC256P-15 RRZ X28HC256PI-15 RR X28HC256PI-15 RRZ X28HC256PM-15 RR X28HC256SI-15 RR X28HC256SI-15 RRZ X28HC256SM-15 RR X28HC256D-12 RR X28HC256DI-12 RR X28HC256DM-12 RR C X28HC256DMB-12 X28HC256EI-12 RR X28HC256EM-12 RR C X28HC256EMB-12 C X28HC256FMB-12 X28HC256J-12 RR X28HC256J-12 ZRR X28HC256JI-12 RR X28HC256JI-12 ZRR X28HC256KI-12 RR X28HC256KM-12 RR C X28HC256KMB-12 X28HC256P-12 RR X28HC256P-12 RRZ X28HC256PI-12 RR 120 ACCESS TIME (ns) 150 TEMP. RANGE (C) -40 to +85 -55 to +125 MIL-STD-883 MIL-STD-883 MIL-STD-883 0 to +70 0 to +70 -40 to +85 -40 to +85 -55 to +125 -40 to +85 -55 to +125 MIL-STD-883 0 to +70 0 to +70 -40 to +85 -40 to +85 -55 to +125 -40 to +85 -40 to +85 -55 to +125 0 to +70 -40 to +85 -55 to +125 MIL-STD-883 -40 to +85 -55 to +125 MIL-STD-883 MIL-STD-883 0 to +70 0 to +70 -40 to +85 -40 to +85 -40 to +85 -55 to +125 MIL-STD-883 0 to +70 0 to +70 -40 to +85 28 Ld CERDIP 28 Ld CERDIP 28 Ld CERDIP 32 Ld LCC (458 mils) 28 Ld FLATPACK (440 mils) 32 Ld PLCC 32 Ld PLCC (Pb-free) 32 Ld PLCC 32 Ld PLCC (Pb-free) 32 Ld PLCC 28 Ld PGA 28 Ld PGA 28 Ld PGA 28 Ld PDIP 28 Ld PDIP (Pb-free)*** 28 Ld PDIP 28 Ld PDIP (Pb-free)*** 28 Ld PDIP 28 Ld SOIC (300 mil) 28 Ld SOIC (300 mil) (Pb-free) 28 Ld SOIC (300 mil) 28 Ld CERDIP (520 mils) 28 Ld CERDIP (520 mils) 28 Ld CERDIP (520 mils) 28 Ld CERDIP (520 mils) 32 Ld LCC (458 mils) 32 Ld LCC (458 mils) 32 Ld LCC (458 mils) 28 Ld FLATPACK (440 mils) 32 Ld PLCC 32 Ld PLCC (Pb-free) 32 Ld PLCC 32 Ld PLCC (Pb-free) 28 Ld PGA 28 Ld PGA 28 Ld PGA 28 Ld PDIP 28 Ld PDIP (Pb-free)*** 28 Ld PDIP N32.45x55 N32.45x55 N32.45x55 N32.45x55 G28.550x650A G28.550x650A G28.550x650A E28.6 E28.6 E28.6 N32.45x55 N32.45x55 N32.45x55 N32.45x55 N32.45x55 G28.550x650A G28.550x650A G28.550x650A E28.6 E28.6 E28.6 E28.6 E28.6 MDP0027 MDP0027 MDP0027 F28.6 F28.6 F28.6 F28.6 PACKAGE PKG. DWG. # F28.6 F28.6 F28.6
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FN8108.2 May 7, 2007
X28HC256 Ordering Information (Continued)
PART NUMBER X28HC256PIZ-12 (Note) X28HC256S-12* X28HC256SZ-12 (Note) X28HC256SI-12* X28HC256SIZ-12 (Note) X28HC256SM-12*, ** X28HC256D-90 X28HC256DI-90 X28HC256DM-90 X28HC256DMB-90 X28HC256EM-90 X28HC256EMB-90 X28HC256FI-90 X28HC256FM-90 X28HC256FMB-90 X28HC256J-90* X28HC256JZ-90* (Note) X28HC256JI-90* X28HC256JIZ-90* (Note) X28HC256JM-90* X28HC256KM-90 X28HC256KMB-90 X28HC256P-90 X28HC256PZ-90 (Note) X28HC256PI-90 X28HC256PIZ-90 (Note) X28HC256S-90* X28HC256SI-90* X28HC256SIZ-90 (Note) X28HC256SI-20T1 *Add "T1" suffix for tape and reel. **Add "T2" suffix for tape and reel. ***Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING X28HC256PI-12 RRZ X28HC256S-12 RR X28HC256S-12 RRZ X28HC256SI-12 RR X28HC256SI-12 RRZ X28HC256SM-12 RR X28HC256D-90 RR X28HC256DI-90 RR X28HC256DM-90 RR C X28HC256DMB-90 X28HC256EM-90 RR C X28HC256EMB-90 X28HC256FI-90 RR X28HC256FM-90 RR C X28HC256FMB-90 X28HC256J-90 RR X28HC256J-90 ZRR X28HC256JI-90 RR X28HC256JI-90 ZRR X28HC256JM-90 RR X28HC256KM-90 RR C X28HC256KMB-90 X28HC256P-90 RR X28HC256P-90 RRZ X28HC256PI-90 RR X28HC256PI-90 RRZ X28HC256S-90 RR X28HC256SI-90 RR X28HC256SI-90 RRZ 200 90 90 120 ACCESS TIME (ns) TEMP. RANGE (C) -40 to +85 0 to +70 0 to +70 -40 to +85 -40 to +85 -55 to +125 0 to +70 -40 to +85 -55 to +125 MIL-STD-883 -55 to +125 MIL-STD-883 -40 to +85 -55 to +125 MIL-STD-883 0 to +70 0 to +70 -40 to +85 -40 to +85 -55 to +125 -55 to +125 MIL-STD-883 0 to +70 0 to +70 -40 to +85 -40 to +85 0 to +70 -40 to +85 -40 to +85 -40 to +85 PACKAGE 28 Ld PDIP (Pb-free)*** 28 Ld SOIC (300 mils) 28 Ld SOIC (300 mils) (Pb-free) 28 Ld SOIC (300 mils) 28 Ld SOIC (300 mils) (Pb-free) 28 Ld SOIC (300 mils) 28 Ld CERDIP (520 mils) 28 Ld CERDIP (520 mils) 28 Ld CERDIP (520 mils) 28 Ld CERDIP (520 mils) 32 Ld LCC (458 mils) 32 Ld LCC (458 mils) 28 Ld FLATPACK (440 mils) 28 Ld FLATPACK (440 mils) 28 Ld FLATPACK (440 mils) 32 Ld PLCC 32 Ld PLCC (Pb-free) 32 Ld PLCC 32 Ld PLCC (Pb-free) 32 Ld PLCC 28 Ld PGA 28 Ld PGA 28 Ld PDIP 28 Ld PDIP (Pb-free)*** 28 Ld PDIP 28 Ld PDIP (Pb-free)** 28 Ld SOIC (300 mils) 28 Ld SOIC (300 mils) 28 Ld SOIC (300 mils) (Pb-free) 28 Ld SOIC (300 mils) Tape and Reel N32.45x55 N32.45x55 N32.45x55 N32.45x55 N32.45x55 G28.550x650A G28.550x650A E28.6 E28.6 E28.6 E28.6 MDP0027 MDP0027 MDP0027 MDP0027 PKG. DWG. # E28.6 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 F28.6 F28.6 F28.6 F28.6
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FN8108.2 May 7, 2007
X28HC256 Pinouts
X28HC256 (28 LD CERDIP, FLATPACK, PDIP, SOIC) TOP VIEW
A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 9 10 11 12 13 14 28 27 26 25 24 23 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
X28HC256 (32 LD PLCC, LCC) TOP VIEW
VCC WE A12 A14 NC A13 A7
X28HC256 (28 LD PGA) BOTTOM VIEW
I/O I/O I/O I/O I/O 1 2 3 5 6 12 13 15 17 18 A8 A9 A11 NC OE A10 CE I/O7 I/O6 I/O A0 0 10 11 A 1 9 A 3 7 A 5 5 A 6 4 V I/O I/O SS 4 7 14 16 19
43 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11
2 1 32 31 30 29 28 27 X28HC256 26 25 24 23
22 X28HC256 8 21 20 19 18 17 16 15
A2 CE A10 8 20 21 X28HC256 A4 OE A11 6 23 22 A12 V CC A 9 2 28 24 A7 3 1 A 14 A8 25
12 22 13 21 14 15 16 17 18 19 20 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5
WE A13 27 26
Pin Descriptions
Addresses (A0 to A14)
The Address inputs select an 8-bit memory location during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers, and is used to initiate read operations.
Data In/Data Out (I/O0 to I/O7)
Data is written to or read from the X28HC256 through the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the X28HC256.
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FN8108.2 May 7, 2007
X28HC256 Pin Names
SYMBOL A0 to A14 I/O0 to I/O7 WE CE OE VCC VSS NC DESCRIPTION Address Inputs Data Input/Output Write Enable Chip Enable Output Enable +5V Ground No Connect
The page write mode can be initiated during any write operation. Following the initial byte write cycle, the host can write an additional one to one hundred twenty-seven bytes in the same manner as the first byte was written. Each successive byte load cycle, started by the WE HIGH to LOW transition, must begin within 100s of the falling edge of the preceding WE. If a subsequent WE HIGH to LOW transition is not detected within 100s, the internal automatic programming cycle will commence. There is no page write window limitation. Effectively the page write window is infinitely wide, so long as the host continues to access the device within the byte load cycle time of 100s.
Write Operation Status Bits
The X28HC256 provides the user two write operation status bits. These can be used to optimize a system write cycle time. The status bits are mapped onto the I/O bus as shown in Figure 1.
I/O DP TB 5 4 3 2 1 0
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The read operation is terminated by either CE or OE returning HIGH. This two line control architecture eliminates bus contention in a system environment. The data bus will be in a high impedance state when either OE or CE is HIGH.
RESERVED TOGGLE BIT DATA POLLING
Write
Write operations are initiated when both CE and WE are LOW and OE is HIGH. The X28HC256 supports both a CE and WE controlled write cycle. That is, the address is latched by the falling edge of either CE or WE, whichever occurs last. Similarly, the data is latched internally by the rising edge of either CE or WE, whichever occurs first. A byte write operation, once initiated, will automatically continue to completion, typically within 3ms.
FIGURE 1. STATUS BIT ASSIGNMENT
DATA Polling (I/O7)
The X28HC256 features DATA Polling as a method to indicate to the host system that the byte write or page write cycle has completed. DATA Polling allows a simple bit test operation to determine the status of the X28HC256. This eliminates additional interrupt inputs or external hardware. During the internal programming cycle, any attempt to read the last byte written will produce the complement of that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx). Once the programming cycle is complete, I/O7 will reflect true data.
Page Write Operation
The page write feature of the X28HC256 allows the entire memory to be written in typically 0.8 seconds. Page write allows up to one hundred twenty-eight bytes of data to be consecutively written to the X28HC256, prior to the commencement of the internal programming cycle. The host can fetch data from another device within the system during a page write operation (change the source address), but the page address (A7 through A14) for each subsequent valid write cycle to the part during this operation must be the same as the initial page address.
Toggle Bit (I/O6)
The X28HC256 also provides another method for determining when the internal write cycle is complete. During the internal programming cycle I/O6 will toggle from HIGH to LOW and LOW to HIGH on subsequent attempts to read the device. When the internal cycle is complete the toggling will cease, and the device will be accessible for additional read and write operations.
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FN8108.2 May 7, 2007
X28HC256 DATA Polling I/O7
WE LAST WRITE
CE
OE VIH I/O7 HIGH Z VOL
VOH X28HC256 READY An An An An
A0 TO A14
An
An
An
FIGURE 2. DATA POLLING BUS SEQUENCE
WRITE DATA
DATA Polling can effectively halve the time for writing to the X28HC256. The timing diagram in Figure 2 illustrates the sequence of events on the bus. The software flow diagram in Figure 3 illustrates one method of implementing the routine.
WRITES COMPLETE?
NO
YES
SAVE LAST DATA AND ADDRESS
READ LAST ADDRESS
IO7 COMPARE? YES
NO
X28HC256 READY
FIGURE 3. DATA POLLING SOFTWARE FLOW
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FN8108.2 May 7, 2007
X28HC256 The Toggle Bit I/O6
WE LAST WRITE
CE
OE
I/O6
*
VOH VOL
HIGH Z
*
X28C512, X28C513 READY
* I/O6 Beginning and ending state of I/O6 will vary. FIGURE 4. TOGGLE BIT BUS SEQUENCE
Hardware Data Protection
LAST WRITE
The X28HC256 provides two hardware features that protect nonvolatile data from inadvertent writes. * Default VCC Sense--All write functions are inhibited when VCC is 3.5V typically. * Write Inhibit--Holding either OE LOW, WE HIGH, or CE HIGH will prevent an inadvertent write cycle during powerup and power-down, maintaining data integrity.
YES
LOAD ACCUM FROM ADDR n
Software Data Protection
COMPARE ACCUM WITH ADDR n
COMPARE OK? YES
NO
The X28HC256 offers a software-controlled data protection feature. The X28HC256 is shipped from Intersil with the software data protection NOT ENABLED; that is, the device will be in the standard operating mode. In this mode data should be protected during power-up/down operations through the use of external circuits. The host would then have open read and write access of the device once VCC was stable. The X28HC256 can be automatically protected during power-up and power-down (without the need for external circuits) by employing the software data protection feature. The internal software data protection circuit is enabled after the first write operation, utilizing the software algorithm. This circuit is nonvolatile, and will remain set for the life of the device unless the reset command is issued. Once the software protection is enabled, the X28HC256 is also protected from inadvertent and accidental writes in the powered-up state. That is, the software algorithm must be issued prior to writing additional data to the device.
X28C256 READY
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
The Toggle Bit can eliminate the chore of saving and fetching the last address and data in order to implement DATA Polling. This can be especially helpful in an array comprised of multiple X28HC256 memories that is frequently updated. The timing diagram in Figure 4 illustrates the sequence of events on the bus. The software flow diagram in Figure 5 illustrates a method for polling the Toggle Bit.
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FN8108.2 May 7, 2007
X28HC256 Software Algorithm
Selecting the software data protection mode requires the host system to precede data write operations by a series of three write operations to three specific addresses. Refer to Figure 6 and 7 for the sequence. The three-byte sequence opens the page write window, enabling the host to write from one to one hundred twenty-eight bytes of data. Once the page load cycle has been completed, the device will automatically be returned to the data protected state.
Software Data Protection
VCC 0V DATA ADDRESS CE tBLC MAX WE BYTE OR AGE AAA 5555 55 2AAA A0 5555 WRITES OK (VCC)
tWC
WRITE PROTECTED
FIGURE 6. TIMING SEQUENCE--BYTE OR PAGE WRITE
WRITE DATA AA TO ADDRESS 5555
WRITE DATA 55 TO ADDRESS 2AAA
Regardless of whether the device has previously been protected or not, once the software data protection algorithm is used and data has been written, the X28HC256 will automatically disable further writes unless another command is issued to cancel it. If no further commands are issued the X28HC256 will be write protected during power-down and after any subsequent power-up. Note: Once initiated, the sequence of write operations should not be interrupted.
WRITE DATA A0 TO ADDRESS 5555 BYTE/PAGE LOAD ENABLED
WRITE DATA XX TO ANY ADDRESS
WRITE LAST BYTE TO LAST ADDRESS
OPTIONAL BYTE/PAGE LOAD OPERATION
AFTER tWC RE-ENTERS DATA PROTECTED STATE
FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA
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FN8108.2 May 7, 2007
X28HC256 Resetting Software Data Protection
VCC
DATA ADDRESS CE
AAA 5555
55 2AAA
80 5555
AA 5555
55 2AAA
20 5555
tWC
STANDARD OPERATING MODE
WE
FIGURE 8. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
WRITE DATA AA TO ADDRESS 5555
Note: Once initiated, the sequence of write operations should not be interrupted.
SYSTEM CONSIDERATIONS
Because the X28HC256 is frequently used in large memory arrays, it is provided with a two line control architecture for both read and write operations. Proper usage can provide the lowest possible power dissipation, and eliminate the possibility of contention where multiple I/O pins share the same bus. To gain the most benefit, it is recommended that CE be decoded from the address bus and be used as the primary device selection input. Both OE and WE would then be common among all devices in the array. For a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. Because the X28HC256 has two power modes, standby and active, proper decoupling of the memory array is of prime concern. Enabling CE will cause transient current spikes. The magnitude of these spikes is dependent on the output capacitive loading of the l/Os. Therefore, the larger the array sharing a common bus, the larger the transient spikes. The voltage peaks associated with the current transients can be suppressed by the proper selection and placement of decoupling capacitors. As a minimum, it is recommended that a 0.1F high frequency ceramic capacitor be used between VCC and VSS at each device. Depending on the size of the array, the value of the capacitor may have to be larger. In addition, it is recommended that a 4.7F electrolytic bulk capacitor be placed between VCC and VSS for each eight devices employed in the array. This bulk capacitor is employed to overcome the voltage droop caused by the inductive effects of the PC board traces.
WRITE DATA 55 TO ADDRESS 2AAA
WRITE DATA 80 TO ADDRESS 5555
WRITE DATA AA TO ADDRESS 5555
WRITE DATA 55 TO ADDRESS 2AAA
WRITE DATA 20 TO ADDRESS 5555
AFTER tWC, RE-ENTERS UNPROTECTED STATE
FIGURE 9. WRITE SEQUENCE FOR RESETTING SOFTWARE
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an EEPROM programmer, the following six step algorithm will reset the internal protection circuit. After tWC, the X28HC256 will be in standard operating mode.
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FN8108.2 May 7, 2007
X28HC256
Absolute Maximum Ratings
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . .-10C to +85C X28HC256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65C to +135C X28HC256I, X28HC256M . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on any Pin with Respect to VSS . . . . . . . . . . . . . -1V to +7V DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commerical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55C to +125C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V 10%
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications
Over Recommended Operating Conditions, Unless Otherwise Specified. LIMITS
PARAMETER VCC Active Current (TTL Inputs) VCC Standby Current (TTL Inputs) VCC Standby Current (CMOS Inputs) Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage NOTES:
SYMBOL ICC ISB1 ISB2 ILI ILO VlL (Note 2) VIH (Note 2) VOL VOH IOL = 6mA IOH = -4mA
TEST CONDITIONS CE = OE = VIL, WE = VIH, All I/O's = open, address inputs = .4V/2.4V levels @ f = 10MHz CE = VIH, OE = VIL, All I/O's = open, other inputs = VIH CE = VCC - 0.3V, OE = GND, All I/Os = open, other inputs = VCC - 0.3V VIN = VSS to VCC VOUT = VSS to VCC, CE = VIH
MIN
TYP (Note 7) 30 1 200
MAX 60 2 500 10 10
UNIT mA mA A A A V V V V
-1 2
0.8 VCC + 1 0.4
2.4
1. Typical values are for TA = +25C and nominal supply voltage. 2. VIL min. and VIH max. are for reference only and are not tested. Power-up Timing PARAMETER Power-up to read Power-up to write NOTE: 3. This parameter is periodically sampled and not 100% tested. SYMBOL tPUR, Note 3 tPUW, Note 3 MAX 100 5 UNIT s ms
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X28HC256
Capacitance
SYMBOL CI/O (Note 9) CIN (Note 9) TA = +25C, f = 1MHz, VCC = 5V. TEST Input/output capacitance Input capacitance CONDITIONS VI/O = 0V VIN = 0V MAX 10 6 UNIT pF pF
Endurance and Data Retention
PARAMETER Endurance Data retention MIN 1,000,000 100 MAX UNIT Cycles Years
AC Conditions of Test
Input pulse levels Input rise and fall times Input and output timing levels 0V to 3V 5ns 1.5V
Symbol Table
WAVEFORM INPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don't Care: Changes Allowed N/A OUTPUTS Will be steady Will change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedance
Mode Selection
CE L L H X X OE L H X L X WE H L X X H MODE Read Write Standby and write inhibit Write inhibit Write inhibit I/O DOUT DIN High Z -- -- POWER active active standby -- --
Equivalent AC Load Circuit
5V
1.92k OUTPUT 1.37k 30pF
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FN8108.2 May 7, 2007
X28HC256
AC Electrical Specifications Over Recommended Operating Conditions, Unless Otherwise Specified. X28HC256-70 PARAMETER Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE LOW to Active Output OE LOW to Active Output CE HIGH to High Z Output OE HIGH to High Z Output Output Hold from Address Change SYMBOL tRC (Note 5) tCE (Note 5) tAA (Note 5) tOE tLZ (Note 4) tOLZ (Note 4) tHZ (Note 4) tOHZ (Note 4) tOH 0 0 0 35 35 0 MIN 70 70 70 35 0 0 40 40 0 MAX X28HC256-90 MIN 90 90 90 40 0 0 50 50 0 MAX X28HC256-12 MIN 120 120 120 50 0 0 50 50 MAX X28HC256-15 MIN 150 150 150 50 MAX UNIT ns ns ns ns ns ns ns ns ns
Read Cycle
tRC ADDRESS tCE CE tOE OE VIH WE tLZ DATA I/O HIGH Z DATA VALID tAA tOLZ tOH tHZ DATA VALID tOHZ
NOTES: 4. tLZ min., tHZ, tOLZ min. and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured with CL = 5pF, from the point when CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven. 5. For faster 256k products, refer to X28VC256 product line.
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X28HC256
Write Cycle Limits
PARAMETER Write Cycle Time Address Setup Time Address Hold Time Write Setup Time Write Hold Time CE Pulse Width OE HIGH Setup Time OE HIGH Hold Time WE Pulse Width WE HIGH Recovery (page write only) Data Valid Data Setup Data Hold Delay to Next Write After Polling is True Byte Load Cycle NOTES: 6. Typical values are for TA = +25C and nominal supply voltage. 7. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 8. tWPH and tDW are periodically sampled and not 100% tested. SYMBOL tWC (Note 7) tAS tAH tCS tCH tCW tOES tOEH tWP tWPH (Note 8) tDV tDS tDH tDW (Note 8) tBLC 50 0 10 0.15 100 0 50 0 0 50 0 0 50 50 1 MIN TYP (Note 6) 3 MAX 5 UNIT ms ns ns ns ns ns ns ns ns ns s ns ns s s
WE Controlled Write Cycle
tWC ADDRESS tAS tCS CE tAH tCH
OE tOES tWP WE tOEH
DATA IN tDS DATA OUT
DATA VALID tDH HIGH Z
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FN8108.2 May 7, 2007
X28HC256
CE Controlled Write Cycle
tWC ADDRESS tAS CE tOES OE tOEH tCS WE tCH tAH tCW
DATA IN tDS DATA OUT HIGH Z
DATA VALID tDH
Page Write Cycle
OE (NOTE 9)
CE tWP WE tWPH tBLC
ADDRESS (NOTE 10)
I/O BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n + 1
LAST BYTE BYTE n + 2 tWC
*For each successive write within the page write operation, A7 to A15 should be the same or writes to an unknown address could occur. NOTES: 9. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation. 10. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE or WE controlled write cycle timing.
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FN8108.2 May 7, 2007
X28HC256
DATA Polling Timing Diagram (Note 11)
ADDRESS An An An
CE
WE tOEH tOES
OE tDW I/O7 DIN = X DOUT = X tWC DOUT = X
Toggle Bit Timing Diagram (Note 11)
CE
WE tOEH OE tDW I/O6 HIGH Z * tWC * tOES
* I/O6 beginning and ending state will vary, depending upon actual tWC. NOTE: 11. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
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FN8108.2 May 7, 2007
X28HC256 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A-B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F28.6 MIL-STD-1835 GDIP1-T28 (D-10, CONFIGURATION A) 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c c1 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.500 MAX 0.232 0.026 0.023 0.065 0.045 0.018 0.015 1.490 0.610 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 12.70 MAX 5.92 0.66 0.58 1.65 1.14 0.46 0.38 37.85 15.49 2.54 BSC 15.24 BSC 7.62 BSC 3.18 0.38 0.13 90o 28 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
E
eA
D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.600 BSC 0.300 BSC 0.125 0.015 0.005 90o 28 0.200 0.060 105o 0.015 0.030 0.010 0.0015
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
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FN8108.2 May 7, 2007
X28HC256 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP ND 0.004 (0.10) C
N32.45x55 (JEDEC MS-016AE ISSUE A)
32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 D D1 MIN 0.125 0.060 0.485 0.447 0.188 0.585 0.547 0.238 28 7 9 MAX 0.140 0.095 0.495 0.453 0.223 0.595 0.553 0.273 MILLIMETERS MIN 3.18 1.53 12.32 11.36 4.78 14.86 13.90 6.05 28 7 9 MAX 3.55 2.41 12.57 11.50 5.66 15.11 14.04 6.93 NOTES 3 4, 5 3 4, 5 6 7 7 Rev. 0 7/98 NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions. 7. ND denotes the number of leads on the two shorts sides of the package, one of which contains pin #1. NE denotes the number of leads on the two long sides of the package.
0.025 (0.64) R 0.045 (1.14)
D2/E2 C L D2/E2 VIEW "A"
E1 E NE
D2 E E1 E2 N ND NE
D1 D 0.020 (0.51) MAX 3 PLCS 0.050 (1.27) MIN
A1 A
0.015 (0.38) MIN SEATING -C- PLANE
0.026 (0.66) 0.032 (0.81)
0.025 (0.64) MIN
0.013 (0.33) 0.021 (0.53) (0.12) M A S -B S D S 0.005 VIEW "A" TYP.
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FN8108.2 May 7, 2007
X28HC256 Ceramic Pin Grid Array Package (CPGA)
G28.550x650A 28 LEAD CERAMIC PIN GRID ARRAY PACKAGE
12
13
15
17
18
11
10
14
16
19 A 0.008 (0.20)
9
8
20
21
7
6
22
23 0.050 (1.27) A
5
2
28
24
25
NOTE: Leads 4, 12, 18, and 26
4
3
1
27
26
Typ. 0.100 (2.54) All Leads
0.080 (2.03) 0.070 (1.78)
0.080 (2.03) 4 Corners 0.070 (1.78) 0.110 (2.79) 0.090 (2.29) 0.072 (1.83) 0.062 (1.57)
Pin 1 Index
0.020 (0.51) 0.016 (0.41)
0.660 (16.76) 0.640 (16.26)
A
A 0.561 (14.25) 0.541 (13.75) 0.185 (4.70) 0.175 (4.44)
NOTE: All dimensions in inches (in parentheses in millimeters). Rev. 0 12/05
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FN8108.2 May 7, 2007
X28HC256 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN8108.2 May 7, 2007
X28HC256 Dual-In-Line Plastic Packages (PDIP)
N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.125 0.014 0.030 0.008 1.380 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 1.565 0.625 0.580 MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 35.1 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 39.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 1 12/00
eA eC
C
e
C A BS
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
0.100 BSC 0.600 BSC 0.115 28 0.700 0.200 -
2.54 BSC 15.24 BSC 17.78 5.08 28 2.93
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 20
FN8108.2 May 7, 2007

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